The present invention relates to a vector processor provided independent of the central processor unit in an information processing system.
A vector processor by the prior art is proposed in Saito et al., "Development of Large General-Purpose Computing System NEC System 1000" in NEC Corporation, NEC RESEARCH & DEVELOPMENT, No. 69, April issue, 1983, pp. 9-13. The integrated array processor (IAP), which is the vector processor in this System 1000, is built into the central processor unit (CPU). This IAP, responding to an operation start instruction and an operand from the CPU, starts an operation. In response to the completion of vector processing by the IAP, the CPU outputs the next operation start instruction. It is difficult, however, for an array processor built into the CPU to perform high-speed processing.
Therefore, it is desirable to provide, independently of the CPU, a vector processor capable of high-speed processing, having a clock cycle equal to an integral multiple of that of the CPU and having an expanded bit width for the processing unit.
In this case, the CPU and the vector processor share the processing functions as follows. The former is responsible for supplying processing instructions and operands to and receiving the results of processing from said vector processor. The latter is responsible for performing processing with the operands and providing the results of processing. For some instructions, the CPU need not receive processing results from the vector processor, such results are used in the vector processor for subsequent processing.
In such a system, in order to enable said CPU and vector processor to operate efficiently and raise the speed of execution, it is also necessary to have the operation by the CPU precede that by the vector processor. For instance in a system in which the CPU is ahead of the vector processor by one operation, the CPU gives an instruction and performs operand loading for the second operation while the vector processor is performing the first. To receive the result of the first operation, the CPU waits for the completion of the vector processor's operation. Having received the result of the first operation by the processor, the CPU gives an instruction and performs operand loading for the third operation. Said processor, since it received the operand for the second operation when it completed the first operation, starts the second operation. When the instruction is such that said CPU need not receive the result of operation, the CPU can have its processing precede that by the vector processor within the limitation of operational precedence.
However, this operational precedence is limited by the CPU's relationship with other hardware. If the processing by the CPU is caused to precede beyond this limitation, the instruction given from the CPU to the vector processor will be lost for a full operation, resulting in the disadvantage that the operation of the CPU and that of the vector processor go out of synchronization and the results of processing become incorrect.